The art of digital integrated circuit implementation in silicon is well established. There are numerous technologies such as Application Specific Integrated Circuits (ASIC), Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLD) which implement digital circuits by means of interconnected cells such as gates, flip-flops and other digital elements. The biggest advantage of these technologies is fast operation caused by parallel activity of all digital elements.
However, the present technologies also have a number of shortcomings that are becoming more noticeable as the cell geometry shrinks and design size increases. For example, the place and route time for such devices increases rather exponentially. The present technologies also require cumbersome and labor intensive critical path timing analysis of the routed designs. This invention eliminates entirely the timing analysis and the design compilation time is linearly proportional to the design size.
The current device architectures that use deep sub-micron silicon technologies require complex analysis of cells and their connections to determine the overall design performance. New physical phenomena are playing larger role at higher cell densities, making the layout analysis continuously more complex. It is becoming now quite apparent that some form of incremental compilation will be necessary for the layout of high density deep sub-micron devices. However, such incremental silicon compilation would require a substantial human effort and involvement, which will slow even more the design process. It is thus another object of this invention to eliminate the device layout, requiring incremental compilation altogether.
Efficient testing of complex devices requires placing additional boundary-scan circuits in the silicon. This makes the design more complex and lowers the effective utilization of silicon surface area. However, since there is no other good way to test the silicon, this process is widely applied to ASIC devices in excess of 100,000 gates. It is yet another object of this invention to provide for effective device testing without the need for any additional boundary scan or similar circuits.
Due to a random nature of cell utilization, relatively large areas of the silicon are set aside to facilitate connections between cells in gate arrays, CPLDs and FPGAs. This lowers the effective utilization of the silicon. The devices built per my invention are based on highly regular memory architecture and do not require design dependent interconnect areas, thus improving the silicon surface area utilization.
The current technologies dissipate a large amount of heat because all circuits operate in parallel. This limits the design size that can be placed on the silicon. This invention describes a parallel-serial circuit operation, which lowers power dissipation and allows considerably higher circuit densities.
The current design methodologies are based more on art than strict mathematical algorithms. As a result, designers must manually tweak some of the circuits for better performance or improved area utilization. This requires high level of expertise, constant employee education and trial and error approach for best results. Another object is to eliminate manual tweaking of designs and lower the expertise demanded from a designer. Since this invention is based on mathematical algorithms, it provides a fully automated design environment, which eliminates manual tweaking of designs and lowers the level of expertise demanded from the designer.
Since the current design tool technology is tuned to the physical phenomena in silicon, designers continuously need to buy newer and more advanced software as technology changes. This invention isolates the designer from changes in the silicon technologies so that one tool set will be able to handle all future silicon process enhancements. Another object is to isolate designs from changes in silicon technology by handling all future silicon process enhancements with one tool set.
The current silicon production growth outstrips design tool capabilities by a large margin. While the silicon technologies allow building devices with tens of millions of transistors, the current commercial design tools limit that number to around ten million transistors. Because of that, the design tools are a major drag on further spread of silicon device applications. However, the fault is not with the design tools but with the way digital circuits are implemented in silicon. The currently used silicon architectures make design tools unnecessarily slow, cumbersome and difficult to use. It is thus the purpose of this invention to provide such silicon architecture that would facilitate fast and simple design tools, requiring minimum learning and no expertise in device architecture.
Another object of this invention is to eliminate the device layout for each new design, requiring tedious and time consuming incremental compilation.
It is yet another object of this invention to provide for effective device testing without the need for any additional boundary scan or similar circuits.
The devices built per my invention are based on highly regular memory architecture and do not require design dependent interconnect areas, thus improving the silicon surface area utilization.
This invention describes a parallel-serial circuit operation, which lowers power dissipation and allows considerably higher circuit densities.
Another object is to eliminate manual tweaking of designs and lower the expertise demanded from a designer.
Another object is to isolate a designs from the applied silicon technologies by handling all future silicon process enhancements with one tool set.
Another object of the invention is to provide silicon architecture that facilitates fast and simple design tools to minimize learning and require no expertise in device architecture.